The present invention relates to a logic circuit and, more particularly, to a technology which is especially effective if used in a bipolar CMOS (which will be shortly referred to as the "Bi.multidot.CMOS") to be packaged in a high speed logic integrated circuit device or the like constituting a high speed computer.
There is a Bi.multidot.CMOS logic circuit which is composed of a pair of output bipolar transistors (as will be shortly referred to as the "transistors") in the shape of a totem pole and a CMOS (i.e., Complementary MOS) circuit for imparting a predetermined logic condition to those output transistors. There is also an ECL (i.e., Emitter Coupled Logic) circuit which is constructed of: a current switch circuit composed basically of differential transistors; and an emitter-follower circuit for transmitting the non-inverted and inverted output signal of the current switch circuit. There is further a high speed logic integrated circuit device which is constructed basically of the Bi.multidot.CMOS logic circuit or the ECL circuit, which may be combined to provide a high speed computer.
The Bi.multidot.CMOS logic circuit is disclosed, for example, in Japanese Patent Laid-Open No. 11034/1984 (corresponding to U.S. Pat. No. 4,890,017). On the other hand, the ECL circuit is disclosed, for example, in FIG. 1, on pp. 1301 to 1306 of "A 23-ps/2.1-mW ECL Gate with an AC-Coupled Active Pull-Down Emitter-Follower Stage" by K. Y. Toh et al. of VOL. 24, No. 5 of IEEE JOURNAL OF SOLID-STATE CIRCUITS issued in October, 1989.
The aforementioned high speed logic integrated circuit device or the like has its scale enlarged so that the circuit components of the logic circuit have a tendency to be further miniaturized and highly integrated. As a result, a problem arises in the degradation of reliability by hot carriers, and the absolute value of the supply voltage has to be reduced. However, this reduction of the absolute value of the supply voltage cannot be effected at will in the Bi.multidot.CMOS logic circuit of the prior art partly because the propagation delay time is longer than that of the ordinary CMOS logic circuit and partly because the amplitude of an output signal is compressed to an extent of the base-emitter voltage of the output transistors. In the ECL circuit of the prior art, moreover, the differential transistors are saturated to block the high speed operations if the absolute value of the supply voltage is about 3 V or less.
In order to cope with those difficulties, there is either an NTL (i.e., Non-Threshold Logic) circuit including a phase divider (or phase splitter) and an output emitter-follower circuit for transmitting an inverted output signal of the phase divider, or the so-called "SPL (i.e., Super Push-pull Logic) circuit (as should be referred to U.S. Pat. No. 4,999,520)", in which the output unit of the NTL circuit is replaced by an active pull-down circuit. In the NTL circuit of the prior art, however, the low power consumption of the high speed logic integrated circuit device is prevented because an operating current is steadily caused to flow in the phase divider and the output emitter-follower circuit. In the SPL circuit, on the other hand, the chip area of the high speed logic integrated circuit device is augmented because of the many circuit elements present. It is also found in each of the foregoing various logic circuits that the high speed logic integrated circuit device and accordingly the high speed computer cannot be given an efficient system structure because the logical functions to be realized are restricted.
Incidentally, an improved SPL circuit was filed as U.S. patent application Ser. No. 669,642 on Mar. 14, 1991 by Usami, one of the present inventors, and now abandoned in favor of the following continuing applications: U.S. patent application Ser. No. 929,917, filed Aug. 17, 1992 as a continuation application thereof (now U.S. Pat. No. 5,237,214); and U.S. patent application Ser. No. 739,195, filed Aug. 1, 1991 as a continuation-in-part application thereof (now U.S. Pat. No. 5,206,546).